A differential data sampler is a circuit configured to receive low voltage swing differential data (for example, from a modulated data stream) at an input and generate full swing or amplified sampled data at an output. The circuit receives a clock signal used to control the sampling instant. In many instances it is important for the circuit to be able to correctly sample the differential data at both the center of the bit and near the bit boundary. However, sampling near the bit boundary can be challenging. One reason for this is that the received differential data may not be well behaved in terms of bit width and bit height. For example, bit width and/or height suppression may be applied against the differential data as the data signal propagates through a low pass transmission channel before being received and sampled. It is accordingly possible for the data sampler circuit, when sampling near the bit boundary, to incorrectly detect a low logic value for the data at a sampling instant where the data in fact has a high logic value (and vice versa).
There is a need in the art for a differential data sampler circuit that can address the foregoing and other problems.